As advanced technologies allow higher density memory devices, power supplies may also be decreasing, making it difficult to optimize the speed at which data in the memory devices may be read. This is especially true for EEPROM and FLASH memory, which utilize high internal voltage supplies for programming and erasing memory cells. The size of high voltage transistors used in programming and erasing does not shrink while other devices in the memory shrink due to the need for such high voltage transistors to continue to handle the high voltages. When not programming or erasing or reading memory cells, the memory may be in a standby mode during which the such high voltages are not generated in order to conserve power and reduce heat generation.
The access time of a memory may depend on the memory cell current during a read operation, and the speed of sense amplifiers that sense the memory cell current. The access time is thus also dependent on the speed of sense amplifiers. The current from a memory cell is provided by applying voltages to a bit line and a word line used to access the memory cell. A boost structure may be used to generate a middle voltage to speed the access, but generation of the middle voltage take time.
In prior memory devices, bit line selection is performed by a bit line select circuit that couples a bit line to a sense amplifier. Each memory cell is coupled to a sense amplifier by a high voltage transistor and a low voltage transistor. To make access quicker, prior solutions focused on increasing the width of high voltage transistors. This led to increased areas and a corresponding decrease in memory density. Further, the supply voltage decreased while the threshold voltage of an N transistor remained the same thing, so bit line voltages became too weak, resulting in bad characteristics on the sense amplifiers. Strong parasitic capacitances due to larger size transistors also resulted.
Word line drivers charge word lines with the help of a vboost structure to start cell current flow. As supply voltages decrease, the drive is too poor to ensure a good discharge of the word line through a transistor. A simple doubler has been used to generate higher voltages on the word line, but even more than double the voltage, such as a tripling of the voltage, may be needed. This may result in a strong increase in the rise time and a commensurate risk of damages on the functionality of a read operation at low Vdd.